This is a homepage for sasasatori.
Computing-In-Memory, RISC-V, AI Accelerator, Embodied Intelligence
Sep. 2021 - now : Institute of Microelectronics of the Chinese Academy of Sciences
Ph.D. in Microelectronics and Solid State Electronics
Advisor: Prof. Feng Zhang
Sep. 2017 - Jun. 2021: Beijing Institute of Technology
Yuan, Y.; Sun, Z.; Yang, Y.; Wang, X.; Li, X.; Ma, C.; Chen, Q.; Tang, M.; Wei, X.; Wu, H.; Wang, H.; Liu, Q.; Chen, C.; Yue, J.; Mak, P.; Zhang, F. “A 28-nm Hybrid-Domain Outer Product-Based Floating-Point SRAM Computing-in-Memory Macro With Logarithm Bit-Width Residual ADC for Edge AI,” in IEEE Journal of Solid-State Circuits, 2026, DOI: 10.1109/JSSC.2026.3668132
Yang, Y.*; Yuan, Y.*; Wang, X.; Li, X.; Wu, H.; Liu, Q.; Tang, W.; Fu, X.; Zhang, F. “A Multicore Programmable Variable-Precision Near-Memory Accelerator for CNN and Transformer Models”, in IEEE Journal of Solid-State Circuits, 2025, DOI: 10.1109/JSSC.2025.3624011. (* Equally contributed authors)
Wu, H.; Cheng, Y.; Li, M.; Zhang, B.; Zhang, R.; Yuan, Y.; Yang, Y.; Yue, J.; Wang, X.; Li, X.; Zhang, F. “A 28-nm 88.3-TFLOPS/W POSIT-Approximate-Calculation-Based Digital Computing-in-Memory Macro Incorporating Final-Cycle Fusion and Joint Skipping”, in IEEE Journal of Solid-State Circuits, 2025, DOI: 10.1109/JSSC.2025.3590632.
Yuan, Y.; Zhang, B.; Yang, Y.; Luo, Y.; Chen, Q.; Lv, S.; Wu, H.; Ma, C.; Li, M.; Yue, J.; Wang, X.; Xing, G.; Mak, P.; Li, X.; Zhang, F. “A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training and Inference”, in International Solid State Circuit Conference, 2025, DOI: 10.1109/ISSCC49661.2025.10904659
Zhu, J.;Yuan, Y.; Nie, L.; Tang, W.; Li, M; Wu, H.; Zhao, X.; Xing, G.; Zhang, F. “A 28nm 75.6KOPS 13nJ Computing-in-Memory Pipeline Number Theoretic Transform Accelerator for PQC”, in IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, DOI: 10.1109/TCSII.2024.3481996
Wu, H.; Cheng, Y.; Yuan, Y.; Yue, J.; Li, X.; Wang, X.; Zhang, F. “A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity”, in IEEE Journal of Solid-State Circuits, 2024, DOI: 10.1109/JSSC.2024.3409356
Yuan, Y.; Yang, Y.; Wang, X.; Li, X.; Ma, C.; Chen, Q.; Tang, M.; Wei, X.; Hou, Z.; Zhu, J.; Wu, H.; Ren, Q.; Xing, G.; Mak, P.; Zhang, F. “A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC”, in International Solid State Circuit Conference, 2024, DOI: 10.1109/ISSCC49657.2024.10454313
Wu. H.; Cheng, Y.; Yuan, Y.; Yue, J.; Fu, X.; Ren, Q.; Luo, Q.; Mak, P.; Wang, X.; Zhang, F. “A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity”, in IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, DOI: 10.1109/TCSI.2023.3325850
Huo, Q.; Yang, Y.; Wang, Y.; Lei, D.; Fu, X.; Ren, Q.; Xu, X.; Qing, L.; Xing, G.; Chen, C.; Si, X.; Wu, H.; Yuan, Y.; Li, Q.; Li, X.; Wang, X.; Chang, M.; Zhang, F.; Liu M. “A computing-in-memory macro based on three-dimensional resistive random-access memory”, in Nature Electronics, 2022, DOI: 10.1038/s41928-022-00795-x
National Scholarship (2025)
Chinese Academy of Sciences President’s Scholarship (2025)
UCAS Merit Student (2024, 2025)
RoboMaster Robotics Competition, North China Region First Award, National Second Award, Team Leader (2021)
China College FPGA Innovation Competition, National Second Award, Team Leader (2020)
China College Integrated Circuit Competition, North China Region First Award, National First Grand Award, Team Leader (2020)
RoboMaster Robotics Competition, North China Region Second Award, National Third Award (2019)
BIT Merit Student (2018)
Address: 3 Beitucheng West Road, Chaoyang District, Beijing, PR China
Email: yuanyiyang@ime.ac.cn
My blog on Cnblog: sasasatori - 博客园 (cnblogs.com)